EFM32G-DK3550【PDF 54/467 页】KIT DEVELOPMENT EFM32 GECKO

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...the world's most energy friendly microcontrollers

Bit

[27:26]

[25:24]

[23:21]

[20:18]

[17:14]

Name

src_inc

src_size

dst_prot_ctrl

src_prot_ctrl

R_power

Description

Note

You must set dst_size to contain the same value that src_size contains.

Set the bits to control the source address increment. The address increment depends on the

source data width as follows:

Source data width = byte

b00 = byte.

b01 = halfword.

b10 = word.

b11 = no increment. Address remains set to the value that

the src_data_end_ptr memory location contains.

Source data width = halfword

b00 = reserved.

b01 = halfword.

b10 = word.

b11 = no increment. Address remains set to the value that

the src_data_end_ptr memory location contains.

Source data width = word

b00 = reserved.

b01 = reserved.

b10 = word.

b11 = no increment. Address remains set to the value that

the src_data_end_ptr memory location contains.

Set the bits to match the size of the source data:

b00 = byte

b01 = halfword

b10 = word

b11 = reserved.

Set the bits to control the state of HPROT when the controller writes the destination data.

Bit [23]

This bit has no effect on the DMA.

Bit [22]

This bit has no effect on the DMA.

Bit [21]

Controls the state of HPROT as follows:

0 = HPROT is LOW and the access is non-privileged.

1 = HPROT is HIGH and the access is privileged.

Set the bits to control the state of HPROT when the controller reads the source data.

Bit [20]

This bit has no effect on the DMA.

Bit [19]

This bit has no effect on the DMA.

Bit [18]

Controls the state of HPROT as follows:

0 = HPROT is LOW and the access is non-privileged.

1 = HPROT is HIGH and the access is privileged.

Set these bits to control how many DMA transfers can occur before the controller rearbitrates.

The possible arbitration rate settings are:

b0000

Arbitrates after each DMA transfer.

b0001

Arbitrates after 2 DMA transfers.

b0010

Arbitrates after 4 DMA transfers.

b0011

Arbitrates after 8 DMA transfers.

b0100

Arbitrates after 16 DMA transfers.

b0101

Arbitrates after 32 DMA transfers.

b0110

Arbitrates after 64 DMA transfers.

b0111

Arbitrates after 128 DMA transfers.

b1000

Arbitrates after 256 DMA transfers.

b1001

Arbitrates after 512 DMA transfers.

b1010 - b1111

Arbitrates after 1024 DMA transfers. This means that no arbitration occurs

during the DMA transfer because the maximum transfer size is 1024.

2011-04-12 - d0001_Rev1.10

54

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